Sorry for the lack of updates recently, life, the universe and everything else has interfered.
I want to discuss the following topics in this post:
Extra features (avoiding feature creep)
Progress on Project Hermes
It’s continuing at a reasonable pace. I am behind schedule but I have defined a list of 15 critical tasks that need to be completed before a prototype PCB can be sent for manufacture. I have currently ticked off 3 items.
A diversion, now a planned task, was the IDE interface. The original idea was to utilise the IDE68K design as-is. This has not proven to be the case. When drawing out the schematic I noticed that a few 68EC020 signals were missing. After re-reading the manual, I noticed a few differences. The MC68000 and MC68EC020 output some signals at different clock phases. So the existing design would need some tweaks. Alexh over at EAB converted the ABEL code to VHDL (my preferred HDL). When I compiled it, targeted at the XC9572, as used originally, it did not fit, it needed 74 macrocells from a 72 macrocell part. As no parts had been ordered at this stage, it was easily swapped to a 144 macrocell XC95144 device, as used for the MIA CPLD.
To verify the IDE interface and eventually the Memory Interface Adaptor (MIA) design, I need a 68020 testbench to stimulate both designs. The last time I wrote a VHDL test bench was back in the advanced VHDL training class, back in January 2012, so I’m a little rusty. One of my personal development aims for this project was to improve my VHDL/CPLD skills.
So what I thought would be an easy tasks, grew in size. I must be confident that the IDE interface and the MIA CPLD will work before committing to hardware. Reading some of the user feedback on the IDE68K design reinforces this decision.
I typically have a few hours a week for my design projects, the little details can easily take the available time but I would rather find them now when it is easier and cheaper to fix them.
Not sure If it has been made clear but the design is intended to fit inside the CD32, similar to the venerable DCE SX32. Indeed, the PCB footprint will be no larger than this, though I expect a smaller PCB.
Pre-orders are not required.
I would not start a project if I could not fund it and I will not accept funding for pre-orders. The current development phase will have 3 prototype cards, that has been funded from the profits made from the current range of Amiga adaptor PCBs I sell. Ordering of critical components has commenced, the first batch arrived today and other components will be ordered shortly.
Extra features (avoiding design creep)
If it seems like I am being very harsh shooting down extra design features, I have good reason, feature creep can kill a project. It will take some time to finish the first 3 prototypes. I have added some expansion connectors to allow me to trial other ideas later but without a prototype PCB, other features are a moot point.
Some features, like making the IDE/compact flash slot accessible from the side of the CD32 are accommodatable adding network interfaces or even an SD card interface add cost and complexity.
Once I have some working prototypes, I can experiment, then other features may get added.
Cost is a big issue for the design. Of the expected £120 retail cost, around £50 of that cost is in the manufacturing of the PCB and assembly of the module. Work is ongoing to lower the module costs.
The most expensive components are:
XC95144 CPLD, SRAM, Compact flash connector and the 5V/3.3V logic. I looked at adding a Real Time Clock, with parallel interface, it would have cost more than the CPLDs!
That’s all for now