Update August 2017, project now on indefinite hold
Project Hermes was the codename for an expansion card for the venerable, Amiga CD32 games console, spurned from discussions on the EAB web-forum http://eab.abime.net/showthread.php?t=72361.
The aim is for this blog to be used to track developments and get feedback from fellow users. This wordpress site will also be used to try out the format and will detail non-amiga projects too. My main website, http://www.ianstedman.co.uk, is still active.
The design aim is to produce a couple of prototype expansion boards that allow the CD32 to function as a a fully fledged computer, akin to the Paravision SX-1 or DCE SX32/Pro expansions from the 1990’s. The idea is to provide an affordable, modern alternative to these units. The author owns a DCE SX-32 Pro unit, which with hard drive cost £600 back in 1997! A new expansion board will cost considerably less than this.
8 MB SRAM
Parallel ATA (IDE) port + Compact flash connector.
Floppy port, capable of accepting Amiga or PC floppy drives and floppy emulators.
Real time clock?
Clockport connector to allow for I/O expansions.
Enable/disable logic + switch, for those old games.
Expected cost, around £120.
The question will inevitably be asked, why no accelerator?
KIS (Keep it Simple).
A CPU upgrade will add extra cost and break compatibility with some games, the CD32 after all is a games console. Yes some games would benefit from a faster CPU but the FPGA accelerator technologies, freely available, in the author’s opinion are not ready for use without adding significant risk to the project.
Why is SRAM used not a SIMM socket?
Stability. Even a slow 70ns SRAM, will operate with zero wait states on a 14 MHz MC68EC020 (71ns)bus that takes 3 clock cycles to do anything. Whilst a SIMM slot would be much cheaper to add than SRAM, £1 compared to around £20 for 8 MB of SRAM, age of devices and support are primary concerns. SIMMS are obsolete technology, you can easily buy them from ebay and some old computer shops. Their reliability and speed grades are unknown. Size and speed detection can be troublesome. By supplying a ready-built system with RAM, you do not have the worry about finding suitable parts, this reduces the support costs.
Future posts will provide a few diagrams of the unit and progress to date. The FPGA/CPLD logic is in development, more on this in a future posting. It is anticipated that the first PCBs will be designed May 2014, building of prototypes will commence around this date. Yeah kind of missed that deadline
Crowd-funding is being considered for this project.