Slow and stedy


It’s been a while since my last post  and as one of the aims was to use a blog to provide more updates, I need to get busy.

Block diagrams are excellent

The design is still progressing, it’s just taking a bit of time. One of the first important steps for me is to sketch a block diagram of the system, here is one I made earlier:


It might not look the most exciting diagram but it helped to plan the design. From this it was easy to get a feel for the number of I/O pins for the CPLDs, it showed me where I need the 5V/3.3V logic translation and what discretes were needed.

The design has three discretes/jumpers. The first is an enable/disable jumper (or switch). If A game refuses to work with the extra RAM, you can easily disable the whole card. PATA should not be affected but is to be confirmed.

There are  another two discretes are related to the floppy drive interface. The first input tells the CPLD if either a PC(default) or Amiga floppy drive is connected. This is so I can crossover the important signals (CHNG/RDY) and generate the RDY signal. The other discrete input/jumper is if a duall floppy drive cable is used with a twist, it will again allow me to crossover signals. The floppy interface by default supports PC floppy drives as they are cheaper to obtain.

The final option is a 4MB/8MB RAM selector. To cut costs, this would allow a system with 4MB of RAM. May not be used.

From this diagram I sketched out (but have not shown here) the top level blocks of the Memory and Interface Adaptor (MIA) CPLD. This helps me plan a logical flow for the CPLD. Without this I would not have thought of some of the extra switch inputs.

Changing CAD software

This might seem crazy and it has delayed me a little bit but I took the decision to change the CAD software I use. Since 2002 I have used Cadsoft EagleCAD, a fine tool I know well. I currently use V5.11, which is stable and does most of what I need. One of the limitations is PCB area. Up until now, a 160x100mm PCB area has been sufficient. This design might be greater than that.

I currently have a standard license, which costs 690 Euros+VAT. To move to the Professional edition, for a larger PCB area, the license is 1385 Euro+VAT!  As a registered user, my upgrade costs are slightly reduced. The software upgrade costs would out-strip any money I make from this project, so a cheaper solution was required, enter DesignSpark PCB.

Designspark has had a learning curve, sometime steep but it was not unexpected. I have had to create a few schematic and layout symbols but that is inevitable and a good chance to learn. The online help is Ok but a bit lacking in some areas (took a while to find how to easily edit existing library symbols and download many of them). No schematic tool is perfect though. In addition to Eagle CAD I also use Mentor Graphics schematic tools in my day job, sometimes I try shortcuts from one tool in another.

One area I do plan to use Designspark PCB for is the 3D modelling and mechanical design. It easily creates a 3D view of the PCB, from within the package. With Eagle I have to run a script, export to Sketchup and render, not as easy as one click. In the future, I will put the Designspark Mechanical training to use and export my PCB into a 3D model.  Ok I need to create a basic model of say a CD32 enclosure and a clockport card but it will help. No pain no gain.

I have some ideas of how to make a product tester, this has helped with the design a little as it made me added a few test signals to the edge connector and also how to easily verify a batch of boards.


Progress to date

This will be asked so I might as well say how it is going.

The basic schematics I had have been re-drawn in Designspark. It was mainly some TTL logic, RAM and a CPLD.

The bulk of the remaining schematic work depends on the MIA CPLD design. This will drive the device pinout, taking into account PCB routing. Future efforts will focus on this device. My CPLD design skills are Ok, they need to improve, one of the aims of this project.

I will not have a prototype PCB by the end of June 2014 as I planned. A finished schematic diagram would be good and a mostly finished CPLD is my aim by the end of June.

There is still some static timing analysis to be done, around the CPU and SRAM interfaces but I need to finish some of this to constrain the CPLD timing.

The plan after it has been tracked is for 2-4 prototypes, they will get comprehensively tested and from there, depending on interest, look at production.

I hope to have another update early July.



Categories: Amiga, Hermes

Component selection


Component selection decisions for project Hermes

I thought I would share some of the decisions made whilst selecting the components for the design and how they impact the overall design, in terms of cost, complexity and testability.

The first big decision is the number and types of CPLD/FPGA devices for the interface logic. The original plan was to use a Xilinx XC9500XL series CPLD. Whilst they are not the most exciting of devices they have a few key benefits:

  • Low cost, around the £5 to £10 unit price in small quantities.
  • Available in density from 36 to 288 Macrocells.
  • 5V tolerant, this reduce the amount of external logic.
  • Available in solderable (for prototype) PQFP SMT packages
  • Work with the free vendor design tools.

Xilinx was selected as my preferred logic vendor as I have previous experience with the devices at both a PCB implementation and at HDL level.

The majority of the design uses 3.3V logic, if the chosen CPLD can be 5V tolerant, it reduces the need for 5V to 3.3V level translation on some input only signals, like the address bus and the control bus. This is not a key feature. The number of macrocells and I/O count was surprisingly more important. The basic IDE interface required 71 I/O pins and 81 macrocells and 137 functional blocks. Factor in the extra I/O for a floppy interface and the address decode for the RAM and you have over 100 I/O pins.

An important selection criteria, for any CPLD (Xilinx, Altera or Lattice) was availability in a PQFP package as I want to avoid the BGA options. These devices tend to be limited to a 208 pin PQFP package, in up to 144 macrocells for Xilinx. Whilst the device may have 208 pins, it may only have  around 100 I/O pins. The safest way to implement all the required logic is to split it across two devices as I do not want to use more than 70% of the resources (excluding pin count) of a device, to give some room for changes/routing. The IDE design is borrowed from the IDE68K project which fills a 72 macrocell CPLD. The existing CPLD design could be re-used as-is and the PCB tracked to suit?
To be decided.

Adding the SRAM memory interface and  autoconfig logic (borrowed from the A608 DRAM controller which takes 22 macrocells, and 32 pins) , into another low cost CPLD seems to be a sensible split. This would be logical to add the clockport interface to.

The beauty of hardware description languages is the ability to ‘fit them’ to target devices and view their resource usage, before purchasing any components. You can also run gate level simulations but that is for another day 😉

It has been glossed over but the memory interface uses SRAM not DRAM. Component availability and simplicity of design were the key points. It is possible to procure new SRAM devices, either the Alliance, AS6C1616-55TIN, a 55ns 16 Mbit (2Mbyte) or the R1LV1616RSA-5SI#B0 could be used. They share a common 48 pin TSOP package, allowing the lowest cost part to be used. A 55ns speed grade is fine when connected to the 14 MHz (69ns) system clock of the CD32’s 68EC020 microprocessor as it takes 3 clock cycles (about 220ns) to do anything. Once the timing diagrams are finished I will publish them here.

A DRAM controller and SIMM socket would be £20-30 cheaper to implement but the lack of new SIMM sticks and the potential headache of supporting multiple , old, and potentially bad, SIMM modules, makes a common SRAM solution easier to support.

The PCB will be a 4 layer board.  The cost differential was £4 per board moving from 2 layer to 4 layer but it makes the tracking so much easier as the inner two layers can be power planes with limited tracking if required. This also facilitates a controlled impedance board, important if ‘245 type buffers are used to translate 5V to 3.3V, as they have 10-20 ohm output drivers, which with appropriate series resistors, will facilitate fixing the signal integrity issues that will occur.

Once the above have been taken into account, the detailed design can begin.

Categories: Amiga, Hermes Tags: Tags: ,

Introducing project Hermes (RIP)


Update August 2017, project now on indefinite hold
Project Hermes was the codename for an expansion card for the venerable, Amiga CD32 games console, spurned from discussions on the EAB web-forum

The aim is for this blog to be used to track developments and get feedback from fellow users. This wordpress site will also be used to try out the format and will detail non-amiga projects too. My main website,, is still active.

The design aim is to produce a couple of prototype expansion boards that allow the CD32 to function as a a fully fledged computer, akin to the Paravision SX-1 or DCE SX32/Pro expansions from the 1990’s.  The idea is to provide an affordable, modern alternative to these units. The author owns a DCE SX-32 Pro unit, which with hard drive cost £600 back in 1997! A new expansion board will cost considerably less than this.


Parallel ATA (IDE)  port + Compact flash connector.
Floppy port, capable of accepting Amiga or PC floppy drives and floppy emulators.
Real time clock?
Clockport connector to allow for I/O expansions.
Enable/disable logic + switch, for those old games.

Expected cost, around £120.

The question will inevitably be asked, why no accelerator?
KIS (Keep it Simple).

A CPU upgrade will add extra cost and break compatibility with some games, the CD32 after all is a games console. Yes some games would benefit from a faster CPU but the FPGA accelerator technologies, freely available, in the author’s opinion are not ready for use without adding significant risk to the project.

Why is SRAM used not a SIMM socket?

Stability. Even a slow 70ns SRAM, will operate with zero wait states on a 14 MHz MC68EC020 (71ns)bus that takes 3 clock cycles to do anything. Whilst a SIMM slot would be much cheaper to add than SRAM, £1 compared to around £20 for 8 MB of SRAM, age of devices and support are primary concerns. SIMMS are obsolete technology, you can easily buy them from ebay and some old computer shops. Their reliability and speed grades are unknown. Size and speed detection can be troublesome. By supplying a ready-built system with RAM, you do not have the worry about finding suitable parts, this reduces the support costs.

What’s next?

Future posts will provide a few diagrams of the unit and progress to date. The FPGA/CPLD logic is in development, more on this in a future posting. It is anticipated that the first PCBs will be designed May 2014, building of prototypes will commence around this date. Yeah kind of missed that deadline

Crowd-funding is being considered for this project.


Categories: Amiga, Hermes, Uncategorized